 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| AN727 Vishay Siliconix High-Frequency, High-Efficiency Buck Converter Design For Multi-Cell Battery Configured Systems Using SI9167 Nitin Kalje INTRODUCTION The SI9167 is a high-frequency synchronous dc-to-dc switching buck regulator, with an operating range suitable for two-cell Li+ battery-powered applications. Capable of operation up to 2 MHz, the SI9167 can be used to supply power amplifiers and to power up baseband circuits in satellite phones. Its high operating frequency reduces the size of inductor and capacitor components, while its low on-resistance internal driver ensures maximum power conversion efficiency. Additional features include an integrated input undervoltage lockout, power on reset, integrated soft start, light load pulse skipping mode selection, synchronization, clock output for master-slave configuration of multiple regulators, uncommitted power-good comparator, and over temperature protection. An output power in excess of 2 W at 3.6 VO is possible in 0.3 square inches. TYPICAL APPLICATION CIRCUIT +VIN 5 - 10 V 1 C1 10 mF 16 V PGND 2 R1* 51 W C1 0.1 mF SI9167 ENABLE/DISABLE PWM/PSM R9* 51 kW 1 2 3 4 5 6 7 8 1.3 V C3 0.1 mF 9 10 SD PWM/PSM VIN VIN POK SYNC CLK GND VREF FB COIL COIL PGND COIL PGND POKIN VO VDD ROSC COMP R3 8.2 kW C5 1000 pF C4 56 pF 20 MBRO520T1 19 18 17 16 15 14 13 12 11 R2 75 kW D1 3.6 V @ 600 mA L1 4.7 mH IHLP2525 C1 10 mF 16 V C9 0.1 mF 7 VOUT 8 PGND R7 105 kW R8 64 kW C6 0.1 mF R4 200 W C7 330 pF R6 12.4 kW R5 22 kW STAR GND CON * Optional FIGURE 1. Typical Application Circuit--Buck Document Number: 70959 07-Jul-99 www.vishay.com S FaxBack 408-970-5600 1 AN727 Vishay Siliconix FUNCTIONAL BLOCK DIAGRAM VDD Positive Supply SD VIN Reference Threshold Generator VREF VO FB COMP 1.3 V Soft-Start Timer UVLO POR System Monitor Bias Generator OTP PWM Modulator 1.0 V Ramp Oscillator COSC PWMIN 0.5 V PWMIN PWM/PFM Select PSMIN PSMIN PSM Modulator - + Drivers COIL SYNC CLK ROSC POKIN POK PWM/PSM Negative Return and Substrate GND PGND FIGURE 2. DESIGN GUIDELINES The following section describes key device features and provides general guidelines for designing a buck regulator with the SI9167. Voltage Mode Control For cellular phone and PDA applications, voltage-mode control provides a number of advantages, including the avoidance of power dissipation in current sensing elements, greater noise immunity (since the PWM signal can be as high as 1 V), and a less complicated single feedback loop to compensate with. The BiCMOS process used in the SI9167 improves voltage-mode performance by increasing the operating frequency and thereby pushing the closed loop bandwidth to www.vishay.com S FaxBack 408-970-5600 + - 1.0 V 0.5 V more than 100 kHz. Since the intended applications for this device involves a battery input, such that rapid changes in voltage level are not involved, there is no need for a fast input dynamic response as offered by current mode control. Oscillator FIGURE 3. Voltage Mode Control 2 Document Number: 70959 07-Jul-99 AN727 Vishay Siliconix In the SI9167, the error amplifier output is compared with the 0.5-V peak-to-peak sawtooth waveform elevated by a 0.5-V offset (Figure 3). The offset provides sufficient noise immunity, even at 2-MHz switching frequencies and 1V/nSec MOSFET switching. The error amplifier has an open loop gain of 60 dB with a 2-MHz unity gain bandwidth. This feature helps to simplify compensation and further increase the closed loop bandwidth. The only external component required to set the oscillator frequency is a resistor at Rosc (pin12). The oscillator generates a "20% tolerance frequency with a "1% resistor. High Frequency Operation Low power dc-to-dc regulator designers must consider both the on-resistance of the switches and the gate charge required to turn them on and off. Conventional MOSFETs need more gate charge per ampere of current rating, while Vishay Siliconix's extremely low gate charge, PWM optimized MOSFET technology offers optimum performance even above 1-MHz switching frequencies. The SI9167 has 180-mW internal drivers and requires a very low gate charge drive, translating into lower switching losses at higher frequencies. Moreover, lower gate charge helps increase the switching speed for a given drive power. This further improves efficiency by reducing crossover losses. For this reason, the SI9167 can achieve up to 93% efficiency even when operating at 1 MHz. Efficiency curves for a 3.6-V buck regulator at various input voltage levels are provided in Figure 4. hysteresis losses in an inductor, as well as ESR losses in capacitors, are the limiting factors in going to higher operating frequencies. Moreover, the effective impedance of capacitors and inductors at higher operating frequencies are dominated by ESL, ESR, and interlayer capacitance, which causes inductors to behave more like capacitors and capacitors to behave more like inductors. The low-profile, high-current IHLP inductor series from Vishay Dale offers excellent high-frequency performance, as do very low-ESR, high-capacity multilayer ceramic capacitors, such that output ripple is inversely proportional to the switching frequency and not determined by the ESR. The X5R series from Murata and the Y5U series from Tokin are recommended dielectrics. Practical Inductor Rdc Rdc Rac Cp L Cp L = dc Resistance of Copper = Skin Effect Related ac resistance = Interlayer Capacitance Ideal Inductance Rac Efficiency, VO = 3.6 V 100 PWM-VIN = 7.2 V 90 PSM-VIN = 5 V PSM-VIN = 7.2 V Efficiency (%) 80 PWM-VIN = 5 V PWM-VIN = 8.4 V Practical Capacitor 70 PSM-VIN = 8.4 V RESR RESR Rp C RESL = Equivalent Series Resistance = Insulation Resistance = Interlayer Capacitance Equivalent Series Inductance 60 RESL 50 10 100 Load Current (mA) 1000 C Rp FIGURE 4. Efficiency vs. Output Load Passive Components Within limits, high switching frequencies reduce the size of passive components. Frequency-dependent skin effect and Document Number: 70959 07-Jul-99 FIGURE 5. www.vishay.com S FaxBack 408-970-5600 3 AN727 Vishay Siliconix VIN = 7.2 V, VO = 3.6 V, IO = 150 mA Ch1: VOUT (200 mV/div) Ch2: Inductor Current (500 mA/div) Ch3: PWM/PSM (High PWM, Low PSM) FIGURE 6. PSM-PWM-PSM Transition PSM-PWM Operation The SI9167 can operate in either fixed-frequency PWM mode or fixed on-time pulse skipping mode (PSM). Switching losses resulting from the gate charge of the driver and internal BICMOS circuitry are fixed irrespective of the output power drawn from the converter. At lower output levels, the percentage of these losses is high, which makes the circuit less efficient. Therefore, at output loads lower than 150 mA, PSM operation is recommended. PSM operation reduces the operating frequency, depending upon the load, which in turn reduces the switching losses proportionally and keeps the efficiency high at all load current levels. output capacitance and ESR. The capacitor must be selected for an acceptable droop in output voltage at a maximum load current in PSM, and is given by the following equation: V O_DROP + I OUT t BLANK ) ESR C OUT (1) Where VO_DROP tBLANK COUT ESR IOUT = = = = = Output droop during Transition (V) Blanking time (S) Output Capacitor (F) ESR of output Capacitor (W) Output Load (A) Inductor Selection Low operating frequencies can become a concern if they are in the audible range. Special care has been taken in the SI9167 to ensure that the operating frequency will always be above 20 kHz in pulse-skipping mode at output load currents as low as 6 mA. A load current of 150 mA is guaranteed in PSM, while PWM mode is used for higher load current operation. In this way, converter efficiency is always optimized. Efficiency versus load plots are provided in figures 14 and 15. A wide selection of inductors is available from vendors such as Vishay Dale, Coiltronix, and Sumida. Major factors to consider include inductance value, saturating current, and equivalent series resistance (RL). Since the SI9167 can be operated at up to 2 MHz, required inductance for a given output capacitor and ripple current could be as low as 1.5 mH, where: Two different sections control the operation of the converter in either PWM mode or PSM. When PWM mode is selected, the PWM control section is active, thereby disabling the PSM control and vice versa. During the PWM-to-PSM transition, there is an overlapping time between the PWM and the PSM circuit activation, which keeps the output voltage from drooping. However, while transitioning from PSM to PWM, there is no such overlap. The time needed to activate the PWM circuit, after the PSM circuit is turned off, is called the blanking time. During this time there are no pulses. This blanking time is typically between 5 to 10 ms. Figure 6 shows the behavior of the output voltage, output, and coil current during the PSMPWM-PSM transition. The sag in the output depends upon the www.vishay.com S FaxBack 408-970-5600 LMIN + dMIN + VINMAX * V DSQP * V OUT ) VR_DROP dMIN 0.72 V OUT ) V R_DROP VINMAX * VDSQP I OUT I OUT Fsw DI (2) V DSQP + 0.42 V R_DROP + R L ) R TRACE 4 Document Number: 70959 07-Jul-99 AN727 Vishay Siliconix Where VINMAX = Maximum input voltage (V) VOUT = Output Voltage (V) VDSQP = Voltage drop across the main switch (V) DI = Max ripple current allowed for acceptable ripple (A) dMIN= Duty ratio at VINMAX. VR_DROP = Resistive drop through inductor and PCB traces (V) IOUT = Rated output current (A) RL = Equivalent Series Resistance (W) RTRACE = Combined resistance of positive and negative output traces (W) Fsw = Oscillator Frequency (Hz) R6 + V R5 OUT (3) V REF *1 The typical value for VREF is 1.3 V. Power_Good Comparator The inverting input is internally connected to the reference voltage of 1.3 V (see functional block diagram, Figure 2). This uncommitted comparator, with about 50 mV hysteresis, is intended to be used to sense the output voltage and raise a high flag once the output voltage Vout reaches its regulation limit. The 50-mV hysteresis at the comparator input is provided while output is transitional from high to low. The output is capable of sourcing 2 mA and sinking 1 mA current. The source current can be increased up to 1 mA by pulling the output high with an external resistor (Figure 1). Use following equation for the POK to switch to high at a VOL and to low at [VOL - VHYSTERESIS]. Refer to Figure 7 when deciding the inductance and frequency. The frequency VS inductance plot assumes a 10-mF ceramic multilayer chip capacitor with a 20-mW maximum ESR and 10-mVp-p output ripple. FSW vs. Inductance 16 14 12 10 L ( m H) 8 6 VIN POK (V) 4 2 0 300 V OL + 1.3 (R7 ) R8) Volts R8 (R7 ) R8) mVolts R8 (4) V HYSTERESIS + 50 500 700 900 1100 1300 1500 1700 1900 (VOL - VHYSTERESIS) (VOL) Fsw (kHz) FIGURE 7. Inductor Value Selection for 10-mF Ceramic Output Capacitor FIGURE 8. VOUT (V) Synchronization Output Voltage Systems using more than one converter for power management functions often face EMC problems. The reflected ripple at the inputs from these independent converters, which operate at different frequencies and phases, can create a wide frequency range of harmonics. Obviously, it is difficult, if not impossible, to eliminate all of these from the emission spectrum. The alternatives are to incorporate a heavy filter at the input of each converter or let all converters oscillate at the same frequency and phase. The divider resistor pair, R5 and R6 in Figure 1 determine the output regulation point. Since R5 is part of the compensation network, it is strongly recommended that R6 be adjusted in order to change the regulation voltage without affecting the loop gain. With fixed R5, R6 can be easily calculated by (3) for the desired output voltage setting. Document Number: 70959 07-Jul-99 www.vishay.com S FaxBack 408-970-5600 5 AN727 Vishay Siliconix With the SI9167, synchronization is possible without the use of any extra components. With the external clock, the circuit synchronizes during the falling edge. More than one SI9167 can be configured in a master-slave mode as shown in Figure 9. The SYNC pin may also be driven from a very stable external system clock signal, which locks the slave frequency within a very tight tolerance. Although synchronization is possible only during PWM, circuit performance is not affected when either the master or slave is in PSM. (Switching frequencies for master, slaves and CLK condition in PSM are provided in Table 1.) In addition, since the SYNC is a high-impedance gate, it does not load the CLK when it is in the high state. IC1 1 2 3 4 5 External Clock 6 7 8 9 10 SD PWM/PSM VIN VIN POK SYNC CLK GND VREF FB COIL COIL PGND COIL PGND POKIN VO VDD ROSC COMP 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 SD IC2 COIL COIL PGND COIL PGND POKIN VO VDD ROSC COMP 20 19 18 17 16 15 14 13 12 11 1 2 3 4 5 6 7 8 9 10 SD IC3 COIL COIL PGND COIL PGND POKIN VO VDD ROSC COMP 20 19 18 17 16 15 14 13 12 11 PWM/PSM VIN VIN POK SYNC CLK GND VREF FB PWM/PSM VIN VIN POK SYNC CLK GND VREF FB Master ROSC Slave ROSC Slave ROSC FIGURE 9. TABLE 1. MASTER AND SLAVE SWITCH FREQUENCIES DURING SYNCHRONIZATION Mode Master PWM PWM PSM PSM Switch Frequency Slave PWM PSM PWM PSM Master CLK_Master CLK_Master PSM_Master PSM_Master Slave CLK_Master PSM_Slave CLK_Slave PSM_Slave Master CLK Pi M Pin High High www.vishay.com S FaxBack 408-970-5600 6 Document Number: 70959 07-Jul-99 AN727 Vishay Siliconix VIN = 7.2 V, VO = 3.6 V, IO = 150 mA Ch1: VOUT (50 mV/div) Ch3: Coil (5 V/div) FIGURE 10. PSM Output Ripple VIN = 7.2 V, VO = 3.6 V, IO = 600 mA Ch1: VOUT (10 mV/div) Ch3: Coil (5 V/div) FIGURE 11. PWM Output Ripple VIN = 7.2 V, VO = 3.6 V, Step IO = 0 to 150 mA Step Load Slew Rate = 1 A/msec Ch1: VOUT (50 mV/div) Ch2: IOUT (100 mA/div) FIGURE 12. Transient Response PSM Mode www.vishay.com S FaxBack 408-970-5600 Document Number: 70959 07-Jul-99 7 AN727 Vishay Siliconix VIN = 7.2 V, VO = 3.6 V, Step IO = 0 to 600 mA Step Load Slew Rate = 1 A/msec Ch1: VOUT (100 mV/div) Ch2: IOUT (500 mA/div) FIGURE 13. Transient Response PWM Mode Efficiency, VO = 3.6 V 100 PWM-VIN = 7.2 V 90 PSM-VIN = 5 V PSM-VIN = 7.2 V Efficiency (%) 80 PWM-VIN = 5 V 100 Efficiency, VO = 7.2 V PSM-VIN = 8.4 V 90 PWM-VIN = 8.4 V PWM-VIN = 8.4 V Efficiency (%) 80 70 PSM-VIN = 8.4 V 70 60 60 50 10 100 Load Current (mA) 1000 50 10 100 Load Current (mA) 1000 FIGURE 14. FIGURE 15. www.vishay.com S FaxBack 408-970-5600 8 Document Number: 70959 07-Jul-99 |
Price & Availability of SI9167
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |